Semiconductor apparatus and method for fabricating the same

ABSTRACT

First, a substrate, on which a plurality of semiconductor devices is formed, is provided. Next, a first etching treatment is carried out to the substrate with a first etching gas comprising CF 4  to form a base trench having a rounded-off upper edge or tapered upper edge. A second etching treatment is carried out to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge. And then, an insulating layer is formed on the substrate to fill up the trench region therewith.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority of Application No.2000-161928, filed May 31, 2000 in Japan, the subject matter of which isincorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates to a semiconductor apparatus, andmore particularly to a method for fabricating a semiconductor apparatushaving a trench region for isolating semiconductor devices in theapparatus.

BACKGROUND OF THE INVENTION

[0003] For isolating semiconductor devices in a semiconductor apparatus,trench isolation technique has been used. According to a conventionalmethod, an SiN layer is formed on a semiconductor substrate; then trenchregions are formed by etching using the SiN layer as a mask. After that,an oxide layer is provided in the trench regions by a CVD process; andthen, the oxide layer is removed by a CMP process.

[0004] According to such a conventional method, sharp corners of thetrench regions may be exposed when the SiN layer is removed. As aresult, characteristics of semiconductor devices may be changed, andelectric field is concentrated at the exposed corners of the trenchregions.

OBJECTS OF THE INVENTION

[0005] Accordingly, an object of the present invention is to provide asemiconductor apparatus in which a trench region is fabricated to havean upper edge or upper corner which is not exposed.

[0006] Another object of the present invention is to provide asemiconductor apparatus in which a trench region is fabricated not tohave sharp upper edge or upper corner.

[0007] Additional objects, advantages and novel features of the presentinvention will be set forth in part in the description that follows, andin part will become apparent to those skilled in the art uponexamination of the following or may be learned by practice of theinvention. The objects and advantages of the invention may be realizedand attained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

[0008] According to a first aspect of the present invention, asemiconductor apparatus includes a substrate on which a plurality ofsemiconductor devices are formed; a mask layer formed on the substrateto have an opening which corresponds to a device isolating region; atrench region formed by etching the substrate using the mask layer as anetching mask; and an insulating layer filled in the trench region sothat an upper edge or upper corner of the trench region is not exposed.

[0009] The upper edge of the trench region may be rounded-off. The masklayer may be formed so that the opening is expanded outwardly to coverthe upper edge of the trench region completely.

[0010] According to a second aspect of the present invention, a methodincludes the steps of: providing a substrate on which a plurality ofsemiconductor devices are formed; performing a first etching treatmentto the substrate with a first etching gas comprising CF₄ to form a basetrench having a rounded-off upper edge or tapered upper edge; performinga second etching treatment to the substrate to form a trench region atthe base trench so that the trench region has a rounded-off upper edge;and forming an insulating layer on the substrate to fill up the trenchregion therewith.

[0011] The first etching gas may include HBr. Preferably, the ratio offlow rate of HBr and CF₄ is between 1:2 and 1:5.

[0012] The first etching gas may further include CH₂F₂. Preferably, theratio of flow rate of CF₄ and CH₂F₂ is between 2:1 and 3:1. Further, theupper edge of the trench region may be rounded off before forming theinsulating layer.

[0013] According to a third aspect of the present invention, a methodincludes the steps of: providing a substrate on which a plurality ofsemiconductor devices are formed; providing a mask layer on thesubstrate to have an opening corresponding to a device isolating region;performing a first etching treatment to the substrate using the masklayer as an etching mask to form a trench region on the substrate;enlarging the opening of the mask layer so that an upper edge of thetrench region are fully exposed; and providing an insulating layer onthe substrate so that the insulating layer extends outwardly from thetrench region to cover the upper edge of the trench region completely.

[0014] Preferably, the opening of the mask layer is enlarged in therange of 300 Å to 500Å in a horizontal direction on the substrate. Theopening of the mask layer may be enlarged by an isotropic etchingprocess.

[0015] Further, a thermal oxidation treatment may be carried out to thesubstrate after enlarging the opening of the mask layer so that theupper edge of the trench region is rounded off.

[0016] A second etching treatment may be carried out to the substrateafter the opening of the mask layer is enlarged so that the upper edgeof the trench region is tapered. In this case, preferably, a thermaloxidation treatment is carried out to the substrate after the secondetching treatment so that the tapered upper edge of the trench region isrounded off.

[0017] The upper edge of the trench region may be rounded off beforeenlarging the opening of the mask layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a cross-sectional view showing a part of a conventionalsemiconductor apparatus.

[0019]FIGS. 2A to 2G are cross-sectional views showing the fabricationsteps according to a first preferred embodiment of the presentinvention.

[0020]FIGS. 3A and 3B are cross-sectional view used for showing shapesof a semiconductor substrate treated in the different ways.

[0021]FIGS. 4A to 4H are cross-sectional views showing the fabricationsteps according to a second preferred embodiment of the presentinvention.

[0022]FIGS. 5A to 5G are cross-sectional views showing the fabricationsteps according to a third preferred embodiment of the presentinvention.

[0023]FIGS. 6A to 6H are cross-sectional views showing the fabricationsteps according to a fourth preferred embodiment of the presentinvention.

[0024]FIGS. 7A to 7H are cross-sectional views showing the fabricationsteps according to a fifth preferred embodiment of the presentinvention.

[0025]FIGS. 8A to 8J are cross-sectional views showing the fabricationsteps according to a sixth preferred embodiment of the presentinvention.

DETAILED DISCLOSURE OF THE INVENTION

[0026] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which formapart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and scope of the presentinventions is defined only by the appended claims.

[0027] For better understanding of the present invention, a conventionaltechnology is first described in conjunction with FIG. 1. According to aconventional method, an SiN layer (not shown) is formed on asemiconductor substrate 102; then trench regions 103 are formed byetching using the SiN layer as a mask. After that, an oxide layer 104 isprovided in the trench regions 103 by a CVD process; and then, an upperportion of the oxide layer 104 is removed by a CMP process.

[0028] According to such a conventional method, sharp corners 103 a ofthe trench regions 103 may be exposed when the SiN layer is removed. Asa result, characteristics of semiconductor devices may be changed, andelectric field is concentrated at the exposed corners 103 a of thetrench regions 103.

[0029] First Preferred Embodiment

[0030]FIGS. 2A to 2G are cross-sectional views showing the fabricationsteps according to a first preferred embodiment of the presentinvention.

[0031] First, referring to FIG. 2A, a PAD oxide layer 2 is formed on thesemiconductor substrate 1 by a CVD process to have a thickness of about200 Å. Next, an SiN layer 3 is formed on the PAD oxide layer 2 by a CVDprocess to have a thickness of about 500 Å to 5000 Å.

[0032] Subsequently, a resist layer is formed on the SiN layer 3 and ispatterned to have openings 4 a corresponding to device isolatingregions, as shown in FIG. 2B.

[0033] Now referring to FIG. 2C, the PAD oxide layer 2 and SiN layer 3are plasma-etched with an etching gas including HBr and CF₄ using theresist pattern 4 as an etching mask to form trench bases 1 b, at whichtrench regions 5 are to be formed. The etching process used in thisembodiment is ICP (Inductively Coupled Plasma) type of etching. In thisembodiment first and second etching processes are carried out to formthe trench regions 5 in the substrate 1. A first etching is carried outunder the following conditions:

[0034] (1) Gas Flow Rate: HBr/CF₄=20/80 scem

[0035] (2) Electric Power to Upper Electrode/Lower Electrode: 700 W/150W

[0036] (3) Pressure: 15 mTorr

[0037] (4) Etching Time: 10 sec

[0038] According to the first etching process, the trench bases 1 b withrounded-off edges 1 a are formed in the substrate 1. CF₄ is included inthe etching gas, so that no sharp corners or upper edges are formed butthe rounded-off edges 1 a are formed. It can be considered that areaction product including fluorine is formed on inner side surfaces ofthe SiN layer 3, and therefore, the etching speed is lowered aroundinside surface of the trench bases 1 b. In contrast, according to aconventional method using an etching gas not including CF₄, trenchregions are formed to have sharp corners of edges.

[0039] Shapes of the rounded-off edges 1 b are different depending onthe ratio of HBr and CF4 in the etching gas. FIG. 3A shows a trenchregion 5 formed by an etching process using an etching gas including HBrand CF₄ at the ration of 4:1. FIG. 3B shows a trench region 5 formed byan etching process using an etching gas including HBr and CF₄ at theration of 1:4. The following is preferable condition for the firstetching:

[0040] (1) Ratio of HBr:CF₄ =1:2 to 1:5

[0041] (2) Electric Power to Upper Electrode: 500 W or higher

[0042] (3) Pressure: 10 to 30 mTorr

[0043] (4) Etching Time: 10 to 20 sec

[0044] After first etching process, a second etching process is carriedout with an etching gas excluding CF₄ to form the trench regions 5 inthe substrate 1, as shown in FIG. 2D. The second etching process iscarried out under the following condition:

[0045] (1) Gas Flow Rate: HBr/O₂=90/5 sccm

[0046] (2) Electric Power to Upper Electrode/Lower Electrode: 600 W/66 W

[0047] (3) Pressure: 5 mTorr

[0048] (4) Etching Time: 85 sec

[0049] The first and second etching processes are carried outcontinuously using the same etching chamber. The trench regions 5 areformed to have a depth of about 2500 Å to 5000 Å. Each of the trenchregions 5 is shaped to have a wider bottom and narrower top. Shaping thetrench regions in that way makes an oxide 6 layer go into the bottom ofthe trench region 5 easily. The first and second etching processes canbe carried out only using the SiN layer 3 as an etching mask afterremoving the resist pattern 4. However, in view of simplicity offabrication steps and deformation of the SiN layer 3, both of the resistlayer 4 and SiN layer 3 are preferably used as an etching mask.

[0050] Next, as shown in FIG. 2E, an embedded oxide layer 6 is formedover the entire surface of the substrate 1 by a CVD process usinghigh-density plasma. The trench regions 5 are filled up with the oxidelayer 6.

[0051] Subsequently, the oxide layer 6 is polished by a CMP process tothe surface level of the SiN layer 3, as shown in FIG. 2F. After that,the SiN layer 3 and PAD oxide layer 2 are removed to form deviceisolating regions, as shown in FIG. 2G.

[0052] As described above, according to the first preferred embodimentof the present invention, the trench regions 5 are formed to haverounded-shaped upper edges, so that concentration of electric field atupper edges of the trench regions can be prevented and characteristicsof semiconductor devices becomes stable and reliable.

[0053] Second Preferred Embodiment

[0054]FIGS. 4A to 4H are cross-sectional views showing the fabricationsteps according to a second preferred embodiment of the presentinvention. In this embodiment, the same and corresponding components tothose in the first preferred embodiment will be represented by the samereference numerals.

[0055] First, referring to FIG. 4A, a PAD oxide layer 2 is formed on thesemiconductor substrate 1 by a CVD process to have a thickness of about200 Å. Next, an SiN layer 3 is formed on the PAD oxide layer 2 by a CVDprocess to have a thickness of about 500 Å to 5000 Å.

[0056] Subsequently, a resist layer is formed on the SiN layer 3 and ispatterned to have openings 4 a corresponding to device isolatingregions, as shown in FIG. 4B.

[0057] Now referring to FIG. 4C, the PAD oxide layer 2 and SiN layer 3are plasma-etched with an etching gas including HBr, CF₄ and CH₂F₂ usingthe resist pattern 4 as an etching mask to form trench bases 1 b, atwhich trench regions 5 are to be formed. The etching process used inthis embodiment is ICP (Inductively Coupled Plasma) type of etching. Inthis embodiment first and second etching processes are carried out toform the trench regions 5 in the substrate 1. A first etching is carriedout under the following conditions:

[0058] (1) Gas Flow Rate: HBr/CF₄/CH₂F₂=20/60/20 sccm

[0059] (2) Electric Power to Upper Electrode: 400 W

[0060] (3) Pressure: 15 mTorr

[0061] (4) Etching Time: 10 sec

[0062] According to the first etching process, the trench bases 1 b withtapered edges 1 c are formed in the substrate 1. The tapered corners 1 care formed when the etching gas includes CF₄ and CH₂F₂ at a rate of 2:1to 3:1.

[0063] After first etching process, a second etching process is carriedout with an etching gas excluding CF₄ to form the trench regions 5 inthe substrate 1, as shown in FIG. 4D. The second etching process iscarried out under the following condition:

[0064] (1) Gas Flow Rate: HBr/O₂=90/5 sccm

[0065] (2) Electric Power to Upper Electrode/Lower Electrode: 600 W/66 W

[0066] (3) Pressure: 5 mTorr

[0067] (4) Etching Time: 85 sec

[0068] The first and second etching processes are carried outcontinuously using the same etching chamber.

[0069] After the second etching process, a thermal oxidation process iscarried out to the substrate 1 at a temperature of 1050° C. to 1100° C.to round off upper corners 5 a of the trench regions 5, as shown in FIG.4E.

[0070] The trench regions 5 are formed to have a depth of about 2500 Åto 5000 Å. Each of the trench regions 5 is shaped to have a wider bottomand narrower top. Shaping the trench regions in that way makes an oxide6 layer go into the bottom of the trench region 5 easily. The first andsecond etching processes can be carried out only using the SiN layer 3as an etching mask after removing the resist pattern 4. However, in viewof simplicity of fabrication steps and deformation of the SiN layer 3,both of the resist layer 4 and SiN layer 3 are preferably used as anetching mask.

[0071] Next, as shown in FIG. 4F, an embedded oxide layer 6 is formedover the entire surface of the substrate 1 by a CVD process usinghigh-density plasma. The trench regions 5 are filled up with the oxidelayer 6.

[0072] Subsequently, the oxide layer 6 is polished by a CMP process tothe surface level of the SiN layer 3, as shown in FIG. 4G. After that,the SiN layer 3 and PAD oxide layer 2 are removed to form deviceisolating regions, as shown in FIG. 4H.

[0073] As described above, according to the second preferred embodimentof the present invention, CH₂F₂ gas is used in the first etchingprocess, so that the tapered corners 1 b are reliably formed with thetrench regions 5. Further, the tapered corners 1 b are rounded-off, andtherefore, concentration of electric field at upper edges of the trenchregions 5 can be prevented and characteristics of semiconductor devicesbecomes stable and reliable.

[0074] Third Preferred Embodiment

[0075]FIGS. 5A to 5G are cross-sectional views showing the fabricationsteps according to a third preferred embodiment of the presentinvention. In this embodiment, the same and corresponding components tothose in the above-described embodiments will be represented by the samereference numerals.

[0076] First, referring to FIG. 5A, a PAD oxide layer 2 is formed on thesemiconductor substrate 1 by a CVD process to have a thickness of about200 Å. Next, an SiN layer 3 is formed on the PAD oxide layer 2 by a CVDprocess to have a thickness of about 500 Å to 5000 Å.

[0077] Subsequently, a resist layer is formed on the SiN layer 3 and ispatterned to have openings 4 a corresponding to device isolatingregions, as shown in FIG. 5B.

[0078] Now referring to FIG. 5C, the PAD oxide layer 2 and SiN layer 3are plasma-etched by a conventional method with an etching gas of HBrusing the resist pattern 4 as an etching mask to form trench regions 5.The first etching process is carried out under the following condition:

[0079] (1) Gas Flow Rate: HBr/O₂=90/5 sccm

[0080] (2) Electric Power to Upper Electrode/Lower Electrode: 600 W/66 W

[0081] (3) Pressure: 5 mTorr

[0082] (4) Etching Time: 85 sec

[0083] After that, an isotropic etching is carried out to the SiN layer3 by a chemical reaction type of etching using H₃PO₄ or downstream typeof plasma etching so that the openings 4 a are enlarged or expandedoutwardly from the trench regions 5, as shown in FIG. 5D. Preferably,the SiN layer 3 is chemically etched using H₃PO₄ to reduce etchingdamage to the silicon substrate 1. The chemical etching may be carriedout using H₃PO₄ at 160° C. for about 10 minutes.

[0084] The trench regions 5 are formed to have a depth of about 2500 Åto 5000 Å. Each of the trench regions 5 is shaped to have a wider bottomand narrower top. Shaping the trench regions in that way makes an oxide6 layer go into the bottom of the trench region 5 easily.

[0085] Next, as shown in FIG. 5E, the embedded oxide layer 6 is formedover the entire surface of the substrate 1 by a CVD process usinghigh-density plasma. The trench regions 5 are filled up with the oxidelayer 6.

[0086] Subsequently, the oxide layer 6 is polished by a CMP process tothe surface level of the SiN layer 3, as shown in FIG. 5F. After that,the SiN layer 3 and PAD oxide layer 2 are removed to form deviceisolating regions, as shown in FIG. 5G.

[0087] The openings defined by the SiN layer 3 and PAD oxide layer 2 areenlarged, so that the oxide layer 6 completely cover all the corners(upper edges) of the trench regions 5, as shown in FIG. 5G. In otherwords, the oxide layer 6 is formed to extend outwardly from the trenchregions 5 onto active regions surrounding the trench regions 5 on thesemiconductor substrate 1. The portions extended on the active regionsprevent that upper edges (corners) of the trench regions 5 are exposedwhen the SiN layer 3 and PAD oxide layer 2 are removed.

[0088] Preferably, the openings defined by the SiN layer 3 are enlargedor expanded by a length of L, 300 Å to 500 Å, and the oxide layer 6 isformed to have a thickness of 300 Å to 500 Å in order to protect theupper edges of the trench regions 5. If the oxide layer 6 has athickness less than 300 Å, the oxide layer 6 might be undesirablyremoved at the upper edges of the trench regions 5 when the SiN layer 3and PAD oxide layer 2 are removed; and as a result, the upper edges ofthe trench regions 5 would be exposed. For that reason, the openingsdefined by the SiN layer 3 are enlarged or expanded by a length of L,more than 300 Å, and the oxide layer 6 is formed to have a thicknesslarger than 300 Å.

[0089] If the openings defined by the SiN layer 3 are enlarged by alength or width more than 500 Å, the width of the SiN layer 3 would betoo short. As a result, the oxide layer 6 may be polished too much.

[0090] As described above, according to the third preferred embodimentof the present invention, the oxide layer 6 is formed so as to cover theupper edges of the trench regions 5 completely; and therefore, reliabledevice characteristics can be obtained.

[0091] Fourth Preferred Embodiment

[0092]FIGS. 6A to 6H are cross-sectional views showing the fabricationsteps according to a fourth preferred embodiment of the presentinvention. In this embodiment, the same and corresponding components tothose in the above-described embodiments will be represented by the samereference numerals.

[0093] First, referring to FIG. 6A, a PAD oxide layer 2 is formed on thesemiconductor substrate 1 by a CVD process to have a thickness of about200 Å. Next, an SiN layer 3 is formed on the PAD oxide layer 2 by a CVDprocess to have a thickness of about 500 Å to 5000 Å.

[0094] Subsequently, a resist layer is formed on the SiN layer 3 and ispatterned to have openings 4 a corresponding to device isolatingregions, as shown in FIG. 6B.

[0095] Now referring to FIG. 6C, the PAD oxide layer 2 and SiN layer 3are plasma-etched by a conventional method with an etching gas of HBrusing the resist pattern 4 as an etching mask to form trench regions 5.The first etching process is carried out under the following condition:

[0096] (1) Gas Flow Rate: HBr/O₂=90/5 sccm

[0097] (2) Electric Power to Upper Electrode/Lower Electrode: 600 W/66 W

[0098] (3) Pressure: 5 mTorr

[0099] (4) Etching Time: 85 sec

[0100] After that, an isotropic etching is carried out to the SiN layer3 by a chemical reaction type of etching using H₃PO₄ or downstream typeof plasma etching so that the openings 4 a are enlarged or expandedoutwardly from the trench regions 5, as shown in FIG. 6D. Preferably,the SiN layer 3 is chemically etched using H₃PO₄ to reduce etchingdamage to the silicon substrate 1. The chemical etching may be carriedout using H₃PO₄ at 160° C. for about 10 minutes.

[0101] The trench regions 5 are formed to have a depth of about 2500 Åto 5000 Å. Each of the trench regions 5 is shaped to have a wider bottomand narrower top. Shaping the trench regions in that way makes an oxide6 layer go into the bottom of the trench region 5 easily.

[0102] Next, a thermal oxidation treatment is carried out to thesemiconductor substrate 1 to round off upper edges 5 a of the trenchregions 5, as shown in FIG. 6E. Such a thermal oxidation treatment is adry type at a temperature of 1050° C. to 1100° C.

[0103] It is known that oxidation characteristics of such a thermaloxidation process not only depend on oxidation condition but also onphysical stress. More precisely, oxidation speed is faster at a flatportion, where physical stress is dispersed, and is slower at a shapeportion, to which physical stress is easily concentrated, such as theupper edges of the trench region. According to a conventional trenchregion, upper edges are covered with an SiN layer, so that the upperedges are hardly oxidized. According to this embodiment, thesemiconductor substrate 1 is oxidized after the SiN layer 3 is withdrawnor retracted backwardly, so that the upper edges 5 a of the trenchregions 5 are rounded off easily without affection of stress of the SiNlayer 3.

[0104] When such a thermal oxidation treatment is carried out, a thermaloxidation layer or coat is formed on the surface of the trench regions5, and at the same time, the rounded-off portions 5 a are formed.

[0105] Next, as shown in FIG. 6F, the embedded oxide layer 6 is formedover the entire surface of the substrate 1 by a CVD process usinghigh-density plasma. The trench regions 5 are filled up with the oxidelayer 6.

[0106] Subsequently, the oxide layer 6 is polished by a CMP process tothe surface level of the SiN layer 3, as shown in FIG. 6G. After that,the SiN layer 3 and PAD oxide layer 2 are removed to form deviceisolating regions, as shown in FIG. 6H.

[0107] The openings defined by the SiN layer 3 and PAD oxide layer 2 areenlarged, so that the oxide layer 6 completely cover all the corners(upper edges) of the trench regions 5, as shown in FIG. 6H. In otherwords, the oxide layer 6 is formed to extend outwardly from the trenchregions 5 onto active regions surrounding the trench regions 5 on thesemiconductor substrate 1. The portions extended on the active regionsprevent that upper edges (corners) of the trench regions 5 are exposedwhen the SiN layer 3 and PAD oxide layer 2 are removed.

[0108] As described above, according to the fourth preferred embodimentof the present invention, the oxide layer 6 is formed so as to cover theupper edges 5 a of the trench regions 5 completely; and therefore,reliable device characteristics can be obtained. In addition, the upperedges 5 a are rounded-off, so that concentration of electrical field atthe upper edges of the trench regions can be prevented.

[0109] Fifth Preferred Embodiment

[0110]FIGS. 7A to 7H are cross-sectional views showing the fabricationsteps according to a fifth preferred embodiment of the presentinvention. In this embodiment, the same and corresponding components tothose in the above-described embodiments will be represented by the samereference numerals.

[0111] First, referring to FIG. 7A, a PAD oxide layer 2 is formed on thesemiconductor substrate 1 by a CVD process to have a thickness of about200 Å. Next, an SiN layer 3 is formed on the PAD oxide layer 2 by a CVDprocess to have a thickness of about 500 Å to 5000 Å.

[0112] Subsequently, a resist layer is formed on the SiN layer 3 and ispatterned to have openings 4 a corresponding to device isolatingregions, as shown in FIG. 7B.

[0113] Now referring to FIG. 7C, the PAD oxide layer 2 and SiN layer 3are plasma-etched by a conventional method with an etching gas of HBrusing the resist pattern 4 as an etching mask to form trench regions 5.The first etching process is carried out under the following condition:

[0114] (1) Gas Flow Rate: HBr/O₂=90/5 sccm

[0115] (2) Electric Power to Upper Electrode/Lower Electrode: 600 W/66 W

[0116] (3) Pressure: 5 mTorr

[0117] (4) Etching Time: 85 sec

[0118] After that, an isotropic etching is carried out to the SiN layer3 by a chemical reaction type of etching using H₃PO₄ or downstream typeof plasma etching so that the openings 4 a are enlarged or expandedoutwardly from the trench regions 5, as shown in FIG. 7D. Preferably,the SiN layer 3 is chemically etched using H₃PO₄ to reduce etchingdamage to the silicon substrate 1. The chemical etching may be carriedout using H₃PO₄ at 160° C. for about 10 minutes.

[0119] The trench regions 5 are formed to have a depth of about 2500 Åto 5000 Å. Each of the trench regions 5 is shaped to have a wider bottomand narrower top. Shaping the trench regions in that way makes an oxide6 layer go into the bottom of the trench region 5 easily.

[0120] Next, another trench etching process is carried out to thesemiconductor substrate 1. Upper corners of the trench regions 5 areexposed, so that the corners are tapered 5 b, as shown in FIG. 7E. Thatis because, etching speed is faster at the corners due to concentrationof electric field.

[0121] Next, a thermal oxidation treatment is carried out to thesemiconductor substrate 1 to round off the tapered edges 5 b of thetrench regions 5, as shown in FIG. 7F, so that rounded-off edges 5 a areformed. Such a thermal oxidation treatment is a dry type at atemperature of 1050° C. to 1100° C. The rounded-off edges 5 a are littlegentler or looser as compared to those in the fourth preferredembodiment.

[0122] Next, as shown in FIG. 7F, the embedded oxide layer 6 is formedover the entire surface of the substrate 1 by a CVD process usinghigh-density plasma. The trench regions 5 are filled up with the oxidelayer 6.

[0123] Subsequently, the oxide layer 6 is polished by a CMP process tothe surface level of the SiN layer 3, as shown in FIG. 7G. After that,the SiN layer 3 and PAD oxide layer 2 are removed to form deviceisolating regions, as shown in FIG. 7H.

[0124] The openings defined by the SiN layer 3 and PAD oxide layer 2 areenlarged, so that the oxide layer 6 completely cover all the corners(upper edges) of the trench regions 5, as shown in FIG. 7H. In otherwords, the oxide layer 6 is formed to extend outwardly from the trenchregions 5 onto active regions surrounding the trench regions 5 on thesemiconductor substrate 1. The portions extended on the active regionsprevent that upper edges (corners) of the trench regions 5 are exposedwhen the SiN layer 3 and PAD oxide layer 2 are removed.

[0125] As described above, according to the fifth preferred embodimentof the present invention, the oxide layer 6 is formed so as to cover theupper edges 5 a of the trench regions 5 completely; and therefore,reliable device characteristics can be obtained. In addition, the upperedges 5 a are rounded-off, so that concentration of electrical field atthe upper edges of the trench regions 5 can be prevented.

[0126] Sixth Preferred Embodiment

[0127]FIGS. 8A to 8J are cross-sectional views showing the fabricationsteps according to a sixth preferred embodiment of the presentinvention. In this embodiment, the same and corresponding components tothose in the above-described embodiments will be represented by the samereference numerals.

[0128] First, referring to FIG. 8A, a PAD oxide layer 2 is formed on thesemiconductor substrate 1 by a CVD process to have a thickness of about200 Å. Next, an SiN layer 3 is formed on the PAD oxide layer 2 by a CVDprocess to have a thickness of about 500 Å to 5000 Å.

[0129] Subsequently, a resist layer is formed on the SiN layer 3 and ispatterned to have openings 4 a corresponding to device isolatingregions, as shown in FIG. 8B.

[0130] Now referring to FIG. 8C, the PAD oxide layer 2 and SiN layer 3are plasma-etched by a conventional method with an etching gas of HBrusing the resist pattern 4 as an etching mask to form trench regions 5.The first etching process is carried out under the following condition:

[0131] (1) Gas Flow Rate: HBr/O₂=90/5 sccm

[0132] (2) Electric Power to Upper Electrode/Lower Electrode: 600 W/66 W

[0133] (3) Pressure: 5 mTorr

[0134] (4) Etching Time: 85 sec

[0135] After that, an isotropic etching is carried out to the SiN layer3 by a chemical reaction type of etching using H₃PO₄ or downstream typeof plasma etching so that the openings 4 a are enlarged or expandedoutwardly from the trench regions 5, as shown in FIG. 8D. Preferably,the SiN layer 3 is chemically etched using H₃PO₄ to reduce etchingdamage to the silicon substrate 1. The chemical etching may be carriedout using H₃PO₄ at 160° C. for about 10 minutes.

[0136] The trench regions 5 are formed to have a depth of about 2500 Åto 5000 Å. Each of the trench regions 5 is shaped to have a wider bottomand narrower top. Shaping the trench regions in that way makes an oxide6 layer go into the bottom of the trench region 5 easily.

[0137] Next, a first thermal oxidation treatment is carried out to thesemiconductor substrate 1 to round off upper edges 5 a of the trenchregions 5, as shown in FIG. 8E. Such a thermal oxidation treatment is adry type at a temperature of 1050° C. to 1100° C.

[0138] After that, an isotropic etching is carried out to the SiN layer3 by a chemical reaction type of etching using H₃PO₄ so that theopenings 4 a are enlarged or expanded outwardly from the trench regions5, as shown in FIG. 8F. When the first thermal oxidation treatment, athin oxide layer is formed on the surface of the silicon substrate 1, sothat the inner surface of the trench regions 5 are not exposed to H₃PO₄directly.

[0139] Next, as shown in FIG. 8G, the embedded oxide layer 6 is formedover the entire surface of the substrate 1 by a CVD process usinghigh-density plasma. The trench regions 5 are filled up with the oxidelayer 6. Preferably, the oxide layer 6 is of porous structure or a layercontaining water or moisture.

[0140] After that, a second thermal oxidation process is carried out tothe silicon substrate 1 to further round off the upper edges 5 a of thetrench regions 5, as shown in FIG. 8H. Preferably, the second thermaloxidation is of wet manner, in which oxidation speed is faster, ratherthan dry manner, in which oxidation speed is slower. Although, the upperedges 5 a of the trench regions are covered with a CVD oxide layer,round-off effect to the upper edges 5 a can forward, because thephysical stress of the CVD oxide layer is lower than that of the SiNlayer 3. The oxide layer is preferably of porous structure to obtainsufficient round-off effect. The oxide layer 6 becomes to have a higherdensity in the second thermal oxidation process.

[0141] Subsequently, the oxide layer 6 is polished by a CMP process tothe surface level of the SiN layer 3, as shown in FIG. 8I. After that,the SiN layer 3 and PAD oxide layer 2 are removed to form deviceisolating regions, as shown in FIG. 8J.

[0142] The openings defined by the SiN layer 3 and PAD oxide layer 2 areenlarged, so that the oxide layer 6 completely cover all the corners(upper edges) of the trench regions 5, as shown in FIG. 8J. In otherwords, the oxide layer 6 is formed to extend outwardly from the trenchregions 5 onto active regions surrounding the trench regions 5 on thesemiconductor substrate 1. The portions extended on the active regionsprevent that upper edges (corners) of the trench regions 5 are exposedwhen the SiN layer 3 and PAD oxide layer 2 are removed.

[0143] As described above, according to the sixth preferred embodimentof the present invention, the oxide layer 6 is formed so as to cover theupper edges 5 a of the trench regions 5 completely; and therefore,reliable device characteristics can be obtained. In addition, the upperedges 5 a are rounded-off, so that concentration of electrical field atthe upper edges of the trench regions can be prevented. Further, thesilicon substrate 1 is not exposed to H₃PO₄, so that stable and reliabledevice characteristics can be obtained.

What is claimed is:
 1. A semiconductor apparatus, comprising: asubstrate on which a plurality of semiconductor devices are formed; amask layer formed on the substrate to have an opening which correspondsto a device isolating region; a trench region formed by etching thesubstrate using the mask layer as an etching mask; and an insulatinglayer filled in the trench region so that an upper edge of the trenchregion is not exposed.
 2. A semiconductor apparatus according to claim 1, wherein the upper edge of the trench region is rounded-off.
 3. Asemiconductor apparatus according to claim 1 , wherein the mask layer isformed so that the opening is expanded outwardly to cover the upper edgeof the trench region completely.
 4. A semiconductor apparatus accordingto claim 3 , wherein the upper edge of the trench region is rounded-off.5. A method for fabricating a semiconductor apparatus, comprising thesteps of: providing a substrate on which a plurality of semiconductordevices are formed; performing a first etching treatment to thesubstrate with a first etching gas comprising CF₄ to form a base trenchhaving a rounded-off upper edge or tapered upper edge; performing asecond etching treatment to the substrate to form a trench region at thebase trench so that the trench region has a rounded-off upper edge; andforming an insulating layer on the substrate to fill up the trenchregion therewith.
 6. A method according to claim 5 , wherein the firstetching gas comprises HBr.
 7. A method according to claim 6 , whereinthe ratio of flow rate of HBr and CF₄ is between 1:2 and 1:5.
 8. Amethod for fabricating a semiconductor apparatus, comprising the stepsof: providing a substrate on which a plurality of semiconductor devicesare formed; performing a first etching treatment to the substrate with afirst etching gas comprising HBr and CF₄ to form a base trench having arounded-off upper edge; performing a second etching treatment to thesubstrate using a second etching gas excluding CF₄ to form a trenchregion at the base trench so that the trench region has a rounded-offupper edge; and forming an oxide layer on the substrate to fill up thetrench region therewith, wherein the ratio of flow rate of HBr and CF₄in the firs etching gas is between 1:2 and 1:5.
 9. A method according toclaim 6 , wherein the first etching gas further comprises CH₂F₂.
 10. Amethod according to claim 9 , wherein the ratio of flow rate of CF₄ andCH₂F₂ is between 2:1 and 3:1.
 11. A method according to claim 9 ,further comp the step of: rounding off the upper edge of the trenchregion before forming the insulating layer.
 12. A method according toclaim 11 , wherein the rounding-off process is carried out by a thermaloxidation treatment to the substrate.
 13. A method for fabricating asemiconductor apparatus, comprising the steps of: providing a substrateon which a plurality of semiconductor devices are formed; performing afirst etching treatment to the substrate with a first etching gascomprising HBr, CF₄ and CH₂F₂ to form a base trench having a taperedupper edge; performing a second etching treatment to the substrate usinga second etching gas excluding CF₄ and CH₂F₂ to form a trench region atthe base trench; performing a thermal oxidation treatment to thesubstrate so that the trench region has a rounded-off upper edge; andforming an oxide layer onto the substrate to fill up the trench regiontherewith, wherein the ratio of flow rate of CF₄ and CH₂F₂ in the firstetching gas is between 2:1 and 3:1.
 14. A method for fabricating asemiconductor apparatus, comprising the steps of: providing a substrateon which a plurality of semiconductor devices are formed; providing amask layer on the substrate to have an opening corresponding to a deviceisolating region; performing a first etching treatment to the substrateusing the mask layer as an etching mask to form a trench region on thesubstrate; enlarging the opening of the mask layer so that an upper edgeof the trench region are fully exposed; and providing an insulatinglayer on the substrate so that the insulating layer extends outwardlyfrom the trench region to cover the upper edge of the trench regioncompletely.
 15. A method according to claim 14 , wherein the opening ofthe mask layer is enlarged in the range of 300 A to 500 Å in ahorizontal direction on the substrate.
 16. A method according to claim14 , wherein the opening is enlarged by an isotropic etching process tothe mask layer.
 17. A method for fabricating a semiconductor apparatus,comprising the steps of: providing a substrate on which a plurality ofsemiconductor devices are formed; providing a mask layer on thesubstrate to have an opening corresponding to a device isolating region;performing a first etching treatment to the substrate using the masklayer as an etching mask to form a trench region on the substrate;enlarging the opening of the mask layer by an isotropic etching processso that an upper edge of the trench region are fully exposed; andforming an insulating layer on the substrate so that the insulatinglayer extends outwardly from the trench region to cover the upper edgeof the trench region completely.
 18. A method according to claim 14 ,further comprising the step of: performing a thermal oxidation treatmentto the substrate after the opening of the mask layer is enlarged so thatthe trench region has a rounded-off upper edge.
 19. A method forfabricating a semiconductor apparatus, comprising the steps of:providing a substrate on which a plurality of semiconductor devices areformed; providing a mask layer on the substrate to have an openingcorresponding to a device isolating region; performing a first etchingtreatment to the substrate using the mask layer as an etching mask toform a trench region on the substrate; enlarging the opening of the masklayer by an isotropic etching process so that an upper edge of thetrench region are fully exposed; performing a thermal oxidationtreatment to the substrate so that the trench region has a rounded-offupper edge; and forming an insulating layer on the substrate so that theinsulating layer extends outwardly from the trench region to cover theupper edge of the trench region completely.
 20. A method according toclaim 14 , further comprising the step of: performing a second etchingtreatment to the substrate after the opening of the mask layer isenlarged so that the upper edge of the trench region is tapered.
 21. Amethod according to claim 20 , further comprising the step of:performing a thermal oxidation treatment to the substrate after thesecond etching treatment so that the tapered upper edge of the trenchregion is rounded off.
 22. A method for fabricating a semiconductorapparatus, comprising the steps of: providing a substrate on which aplurality of semiconductor devices are formed; providing a mask layer onthe substrate to have an opening corresponding to a device isolatingregion; performing a first etching treatment to the substrate using themask layer as an etching mask to form a trench region on the substrate;enlarging the opening of the mask layer by an isotropic etching processso that an upper edge of the trench region are fully exposed; performinga second etching treatment to the substrate so that the upper edge ofthe trench region is tapered; performing a thermal oxidation treatmentto the substrate treatment so that the tapered upper edge of the trenchregion is rounded off; and forming an insulating layer on the substrateso that the insulating layer extends outwardly from the trench region tocover the upper edge of the trench region completely.
 23. A methodaccording to claim 14 , further comprising the step of: performing afirst round off process to the upper edge of the trench region beforeenlarging the opening of the mask layer.
 24. A method according to claim23 , wherein the first rounding-off process is carried out by a dry typeof thermal oxidation treatment.
 25. A method according to claim 23 ,further comprising the step of: performing a second round off process tothe upper edge of the trench regions after the formation of theinsulating layer on the substrate.
 26. A method according to claim 25 ,wherein the second round off process is carried out by a wet type ofthermal oxidation treatment.
 27. A method for fabricating asemiconductor apparatus, comprising the steps of: providing a substrateon which a plurality of semiconductor devices are formed; providing amask layer on the substrate to have an opening corresponding to a deviceisolating region; performing a first etching treatment to the substrateusing the mask layer as an etching mask to form a trench region on thesubstrate; performing a dry type of first thermal oxidation treatment tothe substrate to round off an upper edge of the trench region; enlargingthe opening of the mask layer by an isotropic etching process so that anupper edge of the trench region are fully exposed; performing a wet typeof second thermal oxidation treatment to the substrate so as to furtherround off the upper edge of the trench region; and forming an insulatinglayer on the substrate so that the insulating layer extends outwardlyfrom the trench region to cover the upper edge of the trench regioncompletely.